MOS transistors are found in many modern semiconductor products where switching and/or amplification functions are needed. Many manufacturing processes and techniques have been developed for fabricating MOS devices in semiconductor substrate materials such as silicon and the like. In recent years, the size of transistors and other components have steadily decreased to submicron levels in order to facilitate higher device densities in semiconductor products. At the same time, many new applications have created a need to operate transistors and other semiconductor devices at lower power and voltage levels. Thus, whereas previous MOSFET devices were designed to operate at voltages of 5 or more volts, newer applications may require such devices to operate from DC supplies of around 3 volts down to about 1 volt. In addition, switching speed requirements of MOS transistors continue to increase in order to facilitate faster and improved product performance. Accordingly, efforts continue to be made to design semiconductor devices, such as MOSFET transistors, which occupy less physical space, consume less power, and operate at higher switching speeds and at lower voltages.
MOS transistors include a conductive gate overlying a channel region of the substrate with a thin gate dielectric, typically oxide, therebetween. Source and drain regions of the substrate (sometimes referred to as junction regions) are doped with impurities on opposite sides of the channel, wherein the source/drain regions of nMOS devices are doped with n-type impurities (e.g., As, Sb, P, etc.) and pMOS devices are doped using p-type impurities (e.g., B, Ga, In, etc.). The length of the gate structure overlying the channel is typically referred to as the physical channel length. The source and drain dopants are typically implanted into the silicon substrate using ion implantation systems, wherein the dosage and energy of the implanted ions may be varied depending upon the desired dopant concentration, depth, and profile. The ion dose generally controls the concentration of implanted ions for a given semiconductor material, and the energy level of the beam ions determines the distance of penetration or depth of the implanted ions (e.g., the junction depth).
Following implantation, the dopant atoms in the source/drain regions occupy interstitial positions in the substrate lattice, and the dopant atoms must be transferred to substitutional sites to become electrically active. This process is sometimes referred to as “activation”, and is accomplished by high temperature annealing in an inert ambient such as argon. The activation anneal process also causes diffusion of implanted dopant species downward and laterally in the substrate, wherein the effective channel length becomes less than the physical channel length. As device sizes continue to shrink, the physical and effective channel lengths continue to be scaled downward, wherein short channel effects become significant.
In addition to short channel effects, hot carrier effects are also experienced in short channel devices. For example, during saturation operation of a MOS transistor, electric fields are established near the lateral junction of the drain and channel regions. This field causes channel electrons to gain kinetic energy and become “hot”. Some of these hot electrons traveling to the drain are injected into the thin gate dielectric proximate the drain junction. The injected hot carriers, in turn, often lead to undesired degradation of the MOS device operating parameters, such as a shift in threshold voltage, changed transconductance, changed drive current/drain current exchange, and device instability.
To combat channel hot carrier effects, drain extension regions are commonly formed in the substrate, which are variously referred to as, for example, double diffused drains (DDD), lightly doped drains (LDD), and moderately doped drains (MDD). These drain extension regions absorb some of the potential into the drain and away from the drain/channel interface, thereby reducing channel hot carriers and the adverse performance degradation associated therewith. Referring to prior art FIG. 1, a conventional transistor fabrication process 2 is illustrated beginning at 4, wherein isolation structures are formed in a substrate at 6, and a gate oxide (e.g., gate dielectric) is formed at 8. At 10, a layer of polysilicon is deposited over the gate oxide, and is then patterned at 12 to form a polysilicon gate structure.
Offset spacers may optionally be formed on either side of the gate structure at 13 to guide an implant that is performed at 14, wherein drain extension regions are implanted. Typically, the LDD implant at 14 is a fairly low concentration dopant implantation process, which may also use the edge of the patterned gate structure as an implantation mask, while for MDD implantations the use of the offset spacers provided at 13 may be advantageous. Spacers are then formed at 18 along the sidewalls of the gate structure, and a second implantation (e.g., sometimes called a “source/drain implant”) is performed at 20 using a higher dopant concentration and implantation energy to form the source/drain junction regions.
An activation anneal is then performed at about 1050 degrees C. at 22 to activate the implanted dopant in the drain extensions and the source/drain regions, and also to cause diffusion or migration of dopant downward and laterally in the silicon. Thus, drain extension regions and source/drain regions are provided, which partially overlap one another in the substrate. Typically, the drain extension regions extend downward to a somewhat shallow depth and laterally to or under the gate structure, whereas the deeper source/drain regions are laterally spaced from the gate (e.g., by about the sidewall spacer width). The gate and source/drain regions are then silicided at 24 and back-end interconnect processing is performed at 26 before the method 2 ends at 28.
As a result of the two implantations at 14 and 20, a dopant gradient is established across the junction from the source/drain region of the junction to the drain extension region adjacent the channel, sometimes referred to as a graded junction. The drain extension region operates to assume a substantial portion of the entire voltage drop associated with saturation operation at the drain junction, while the more heavily doped source/drain region forms a low resistivity region suitable for enhanced contact conductivity. Further, the source/drain dose is implanted at a higher energy to produce deeper source/drain junctions (deeper than the extension regions) and thereby to provide better protection against junction spiking.
As CMOS devices are scaled down to support future technologies, it has become increasingly problematic to proportionately scale down the depth and gradient of source/drain extension regions. As a result in part, lightly doped drain LDD extensions have recently given way to moderately doped MDD and highly doped drain extensions HDD, wherein the drain extension depths are becoming smaller (e.g., shallower). The recent trend is toward shallower junctions with lower sheet resistance, wherein reducing sheet resistance facilitates higher drive currents (e.g., improved threshold voltage transistor performance), and faster switching times. Shallower junctions reduce short channel effects, facilitating continuing efforts at scaling MOS transistors to smaller and smaller dimensions, both lateral and vertical scaling.
After implantation of such drain extension regions, prior art annealing has been carried out at low temperatures (e.g., <600° C.) for a substantial period of time, leaving behind considerable end-of-range damage to the crystal lattice boundaries. Prior attempts to anneal out this damage using subsequent anneals in conventional apparatus may result in profile degradation (e.g., loss of dopant gradient abruptness).
The amount of dopant activation in the drain extensions plays a role in determining the sheet resistance thereof, wherein increasing the dopant activation (e.g., lowering the sheet resistance) serves to lower parasitic resistance within the source to drain path. Thus, there is a need for fabrication techniques for MOS type transistors, by which improved epitaxial recrystalization of the source and drain extensions can be facilitated in the manufacture of semiconductor devices.